IBM Research Unveils Test Device for Next-Gen Computer Chips

Dr. Michael Liehr (left) of SUNY Poly CNSE and Bala Haran (right) of IBM Research inspect a wafer comprised of 7nm (nanometer) node test chips in a clean room in Albany, NY. Source: IBM

Semiconductor researchers have produced the industry’s first 7 nm node test chip with functioning transistors. This first step into the next generation of computer chips could eventually put more than 20 billion transistors onto an integrated circuit the size of your fingernail.

The leap forward required the development of several new processes, materials and configurations, including the significant step of integrating extreme ultraviolet lithography in several stages of manufacturing. Photolithography is a semiconductor processing technique used to pattern the different components of a circuit, using light and light-sensitive chemicals to either mask or remove sections of material as the computer chip is built up layer by layer. 

The shorter wavelength of extreme UV light reproduces the pattern designs in finer resolutions than current systems and with smaller gaps between components. Other feats, such as chips stacked with pitches of less than 30 nm and silicon germanium channels that improve transistor speeds, are also industry firsts.

Although the chips are nearly twice as dense as the current advanced technology, this doesn’t mean a reprieve for the semiconductor industry. The chips are only testing devices and commercial manufacturing will likely be several years away. Furthermore, the new devices brought about by miniaturization are influencing new benchmarks for designers and manufacturers.

For the last two decades, the International Technology Roadmap for Semiconductors (ITRS), produced by working groups of international semiconductor industry associations, has provided direction on barriers to maintaining Moore’s Law 15 years into the future and assessed the state of research on potential solutions. However, half a century after Moore’s original observation of exponential increases in transistor density, the industry has recently proposed a reframing of their mission.

Previously, technology advances in computing drove increased miniaturization and lower costs for the device market. However, the increased popularity of smartphones and other products are now reversing some of the driving forces, dictating new metrics with which the manufacturing process can challenge itself. The proposal, referred to as ITRS 2.0, was announced in late 2014 and describes potential metrics such as number of pixels, board area and data transfer rates. Scaling to accommodate these other important metrics will provide an ongoing challenge to researchers.

The work was the result of an industry-university collaboration led by IBM Research, partnered with GlobalFoundries, Samsung and SUNY Polytechnic Institute. For more information, click here.