The technique also has implications for the development of ultra low-power, high-speed computing devices known as tunnelling transistors, as well as the integration of optical components into computer chips.
Today, computer chips are made by stacking layers of different materials and then etching patterns into them. In contrast, this new technique allows different materials to be deposited in the same layer, enabling chips to be built with working versions of all the circuit components necessary to produce a general purpose computer.
The layers in the experimental chip are extremely thin, between one and three atoms thick. This could lead to manufacturing thin, flexible, transparent computing devices which could be laminated onto other materials.
“The methodology is universal for many kinds of structures and offers us tremendous potential with numerous candidate materials for ultrathin circuit design," said Xi Ling, one of the paper’s co-authors.
“It's a brand new structure, so we can expect some new physics,” added Yuxuan Lin, the paper’s other author.
Two Very Different Materials in One Computer Chip
Computer chips are normally built from crystalline solids, the atoms of which are arranged in a regular geometric pattern known as a crystal lattice. Only materials with closely matched lattices can be deposited laterally in the same layer of a chip.
The experimental chip, however, uses two materials with very different lattice sizes: molybdenum disulphide and a form of graphene with a single atom-thick layer of carbon.
This manufacturing technique generalizes to any material that combines elements from groups six and sixteen on the periodic table. Many of these compounds are semiconductors and exhibit useful behavior in extremely thin layers.
Graphene was chosen as the second material due to its many remarkable properties, such as strength and electron mobility. These features make it an excellent candidate for use in thin-film electronics and other nanoscale electronic devices.
The process of assembling this new chip begins by depositing a graphene layer on a silicon substrate. Then the layer is etched in the regions where the molybdenum disulfide layer is needed. A solid PTAS (perylene- 3,4,9,10-tetracarboxylic acid tetra potassium salt) bar is placed at one end of the substrate.
The PTAS is heated, followed by flowing a gas across it and the substrate. This gas carries PTAS molecules that stick to the exposed silicon, but not to the graphene. Where the PTAS molecules do stick, they catalyze a reaction with another gas that causes a layer of molybdenum disulfide to form.
Promising Future for Tunneling-Transistor Processors
This new technology opens the door for a promising future of more powerful computing if it can be used to produce tunneling-transistor processors. Tunneling transistors can operate at very low power and could achieve very high processing speeds.
“The MIT team demonstrated that controlled stitching of two completely different, atomically thin 2-D materials is possible. The electrical properties of the resulting lateral heterostructures are very impressive," commented Philip Kim, physics professor at Harvard.
The research is published in the journal Advanced Materials.