How to Build Nanoelectronic Devices Atom by Atom

An illustration of the complexities of considering defects, vacancies, dopants and impurities within atomic structure. The image shows nine of a possible 7,140 configurations for an example of 36 central atoms with only three defects. (Image courtesy of Yu Zhu and Lei Liu.)

As transistors continue to shrink in accordance with Moore’s Law, it becomes increasingly difficult for engineers to describe their behavior. Once you reach the atomic level, electrons begin to behave more like waves than particles, which can cause existing device models to become inadequate. In fact, with IBM’s success in fabricating 7-nm silicon channels (a width of about 50 atoms), we’ve officially reached this level.

That’s not to say that we’ve reached the end of our engineering ingenuity. There are two general approaches to the problem of modeling atomic level transistors: the top-down approach and the bottom-up approach. Each approach is complementary to the other, but the bottom-up approach is extremely useful for emerging atomic-scale devices. That’s why this approach is considered in a new textbook, called Atomistic Simulation of Quantum Transport in Nanoelectronic Devices, which aims to address the growing field of computational nanoelectronics.

Building Nanoelectronic Devices from the Bottom Up

The top-down approach to modeling nanoelectronic devices requires the inclusion of more and more parameters in our current models so as to capture the small scale atomic effects that could previously be ignored. Unfortunately, the number of parameters required follows the same exponential pattern of Moore’s Law: the number doubles every 18 months.

The bottom-up approach ignores our current models altogether and builds up new models from first principles. The basic idea is to simulate nanoelectronic devices one atom at a time. This makes for a general method of modeling atomic devices using the principles of quantum mechanics and nonequilibrium statistics, a more elegant solution than constantly augmenting existing models.

Just because the bottom-up approach is elegant, however, doesn’t mean that it’s easy. Using this approach involves an in-depth knowledge of a wide range of topics including electronic engineering, condensed matter physics, applied mathematics and computer science. To make it more tractable, there are a number of software tools that take the bottom-up approach in simulating nanoelectronic devices, such as Atomistic Tool Kit, NanoDsim and OpenMX.

Researchers and engineers wanting to develop their own tools have, until now, been left to their own devices (pun intended). The new textbook has been written to consolidate all the relevant knowledge necessary to simulate nanoelectronic devices from the bottom up. Specifically, the textbook opens up the “black box” of the commercial software NanoDsim (Nanoelectronic Device Simulator) in order to demonstrate the theory behind it as well as its numerical and computational implementation, while providing the affiliated source code as a starting point for further research.

An illustration of a two-probe system, one of the two types of systems that NanoDsim can simulate. The left and right leads are semi-infinite crystals with applied external voltages and the central region contains the nanostructure under investigation. The three yellow dots mark a possible configuration of disorder sites. (Image courtesy of Yu Zhu and Lei Liu.)

There are limitations to the bottom-up approach, however. For starters, the computational cost is much higher than that of the top-down approach. Beyond resource concerns, there are theoretical limitations to bottom-up models. Scattering mechanisms are either neglected or crudely approximated and the theory doesn’t accurately describe subtle interfaces or strongly correlated materials.

In spite of these challenges, the new textbook provides an unprecedented resource for engineers designing nanoscale devices. You can learn more about it here.