An image of IBM's 5nm silicon nanosheet chip. (Image courtesy of IBM.)
Today, state-of-the-art chips are comprised of transistors with gates that are 10 nm long. This gate size determines exactly how many transistors can fit on a certain sized chip, essentially limiting the processing power of, say, a fingernail-sized component.
Following Moore’s Law, chip makers have expected that they can double the number of transistors on a chip every two years, but that means reducing the size of transistor gates by half every 24 months. Although Moore’s Law has been prophetic for decades, chip makers have started to run into issues with building ever more complex transistor gates.
In traditional chip manufacturing, chips are built using a FinFET architecture. Although it’s true that FinFET chips can be built with 5-nm gates, reducing the space between FinFET gates will not deliver improved current flow, which translates into better performance.
IBM’s new method for building chips seems to upset that issue, putting Moore’s Law back on good footing.
To make their 5-nm chips, engineers use extreme ultraviolet lithography (EUV) to write patterns onto stacked sheets of silicon nanosheets. By using EUV, ultra-fine details can be etched into the chip, closing the gap between gates from the state-of-the-art 7 nm to 5 nm.
Engineers believe this “can deliver 40 percent performance enhancement at fixed power, or 75 percent power savings at matched performance.”
According to IBM, “The resulting increase in performance will help accelerate cognitive computing, the Internet of Things and other data-intensive applications delivered in the cloud. The power savings could also mean that the batteries in smartphones and other mobile products could last two to three times longer than today’s devices before needing to be charged.”