Ferroelectrics, Negative Capacitance and the Future of Transistors

The IT industry pumps out 2 percent of global CO₂ emissions, a figure on par with aviation. That equates to around 7 percent of the world’s electricity, a figure predicted to double by 2030. A solution to IT’s hefty carbon footprint could be found in Negative Capacitance Field-Effect Transistors (NC-FETs), which have the potential to revolutionize the microprocessor industry.

The NC-FET was hypothesized in 2007 by Sayeef Salahuddin and Supriyo Datta. In the ensuing 10 years, NC-FETs were steadily researched in universities, but never made it out of the lab. New technologies weren’t needed—silicon transistors could be shrunk relentlessly, and more transistors could be crammed onto a smaller chip. However, it looks like the party is over.Silicon transistors are approaching their fundamental physical limits, and major players like Global Foundries are investigating ways to augment chip design without having to rewrite the book. NC-FETs could be silicon’s savior and prolong the improvement of microprocessors well into the 2030s. We might even see improvements in clock speed, a boon for those finite element analysis and computational fluid dynamics engineers who are screaming for more processing grunt.

The Semiconductor

First, a brief explanation of transistors. The semiconductor in transistors is a sandwich of two differently doped forms of silicon. Doping means that approximately one in a million of the silicon atoms are replaced with a different element, like boron or phosphorous.

Each silicon atom has four electrons in its outer shell and bonds to four other silicon atoms.That means a pure silicon lattice has no free electrons and is a poor conductor of electricity. If a photon were to hit pure silicon, it would need an energy of around 1eV to break the covalent bonds between the silicon atoms and liberate an electron. By doping silicon with other elements,this value can be altered.Phosphorus-doped silicon requires 1/40 of an eV to liberate an electron and allow charge to flow.

Replacing one in a million of the silicon atoms with a phosphorus atom creates what’s called an n-type semiconductor. Phosphorus has one more electron than silicon, so when a silicon atom is replaced with a phosphorus, there is one extra electron per million atoms (electrons are negatively charged, hence the name “n-type”). The extra electron can be donated to other atoms and allow charge to flow.

Conversely, boron has one fewer electron than silicon. Silicon doped with boron is a p-type semiconductor because, you guessed it, it’s positively charged. The positive charges present in a p-type semiconductor are referred to as holes. The holes created by boron doping can be thought of charge carriers like electrons, but which move toward the positive terminal rather than the negative.

By sandwiching a layer of boron-doped silicon between two layers of phosphorus-doped silicon, you have the makings of a bipolar transistor.Where the p- and n-type materials touch, phosphorus electrons fill boron holes, and a so-called depletion layer, where the net charge is zero, is created.

In their off state, transistors act like a two-way diode—current can’t flow in either direction. Whatever direction you apply a voltage potential, one of the depletion layers will grow and prohibit current flow.

Transistors control the depletion layer by adding a second power source called the base (or gate in the case of Field Effect Transistors[FETs]). Putting an electric potential across the base shrinks the depletion layer. If the depletion layer shrinks enough, electrons can flow across the substrate and turn on the transistor. Turn the base off, and the depletion layer is restored so no current can flow.

FETs utilize similar principles, though are slightly different in structure.

Problems Facing Chipmakers

Though this isn’t an exhaustive list,here are a few examples of the problems facing chipmakers:

Leakage. Shrinking transistors cause their off-state current (I_off) to increase. This is the current that flows across the silicon substrate when no voltage is on the base.This is wasted current known as leakage. Leakage is converted to heat and extracted from the CPU. I_off determines the power consumption of the chip while idle, and has steadily been increasing as transistors have been shrinking.

One of the advantages of multicore processors is that they can reduce leakage by turning off cores not in use, lowering idle leakage. However, when the cores are activated, leakage occurs again.

Voltage not reducing with chip size. A threshold voltage (V_thr) is required at the base to shrink the depletion layer enough to turn the transistor on. In each generation of CPUs, V_thr has decreased, but it hasn’t scaled proportionally with transistor size. This is a problem because the power usage of the chip is proportional to the square of the voltage. Thus, a situation is created whereby there are more transistors with a similar voltage switching in a smaller area. The power density of chips is therefore increasing, and it is becoming more difficult to keep chips cool. This is illustrated by the complexity of modern CPU coolers. You used to be able to just whack a block of metal and an 8cm fan on a high-end CPU, and it would run well. Nowadays you need something that has been designed for the job.

Small-channel effects. At sub-7nm transistor sizes, short-channel effects become increasingly problematic. This is where the channel of an FET has a similar size as the depletion layer. At this scale, quantum phenomena such as tunneling become increasingly probable. It appears that the only way around this is new architectures—merely shrinking transistors is no longer an option. This is where ferroelectrics and negative capacitance could come in.

In summary, the current transistors use while idling is increasing, and they are reaching sizes where quantum phenomena become dominant. It is debatable whether existing transistor techniques can overcome these problems. However, this paper from 1999 suggested that silicon transistors were only a few generations away from being impractical. Twenty years later they are still here, so it’s not easy to predict the future.

Understanding Ferroelectrics and Negative Capacitance

What are ferroelectric materials? Firstly, a ferroelectric material has nothing to do with iron. In a ferroelectric material, its polarization (separation of positive and negative charges) varies nonlinearly with voltage. Thus, a small change in applied voltage can create a large change in polarization. This contrasts with increasing the voltage across a typical capacitor where polarization will change linearly.

The nonlinear nature of ferroelectric materials means they can spontaneously polarize at a specific voltage, called the coercive voltage. By exploiting a ferroelectric’s spontaneous polarization, it is possible to observe negative capacitance, which means when the voltage across the material increases, the charge in the material goes down and vice versa. Negative capacitance arises due to how atoms move within the lattice of a material and is beyond the scope of this article.

Negative capacitance is a transient phenomenon, meaning that it exists only over a small voltage range. However, it is possible to stabilize negative capacitance and use it in transistors to reduce the base voltage they require to switch on. This, in turn, alters many other characteristics of the transistor.

How adding a ferroelectric layer reduces gate voltage. There are many ways to incorporate ferroelectric materials into transistors, and they function in similar ways. We will consider just one: a ferroelectric layer between the gate and the silicon substrate.

The ferroelectric material can improve the efficiency of a transistor by amplifying the gate voltage. This reduces the V_thr required to switch on the transistor and therefore decreases the transistor’s power usage.

In a traditional FET, when a gate voltage (V_G) is applied, some of that voltage is lost across the silicon semiconductor(φ_s) and some across the insulator (V_ins). Put together, V_G = V_ins + φ_s.

If the insulator is replaced with a ferroelectric layer, then when you apply a voltage at the gate, the voltage in the silicon will be larger than the voltage at the gate due to the negative capacitance of the ferroelectric layer.

If V_G = V_f + φ_s, and a V_gof 1V is applied, the ferroelectric chucks out a V_f of–0.5V, and the voltage in the semiconductor will be 1.5V. This is essentially how the ferroelectric amplifies the gate voltage.

This small adjustment causes a cascade of changes in transistors, which the following section details.

How Adding a Ferroelectric Layer Changes Transistors

The best way to understand how a ferroelectric layer alters transistors is to look at something called the subthreshold slope, which shows how the current across the transistor varies with the voltage at the gate.

The inverse of the subthreshold slope is the subthreshold swing (S), measured in mV/decade (which means a certain voltage at the gate is required to increase the current flow from the source to drain by 10 times). For traditional FETs, the minimum S is 60mV/decade. However, realistic values are closer to 80 to 120mV.

The figure above shows a blue line, which represents a traditional transistor, and red one, representing a negative capacitance transistor. The red line is steeper, which means the gate voltage required to reach V_thr (the transistor switching voltage) is reduced. While you can run a transistor at V_thr, it will be extremely slow, so they tend to run at higher voltages.

At the top of the graph, you’ll see that V_sat(the voltage required to have maximum current flowing in the channel) in the NC-FET is reduced. Hurrah! This means we can run our transistor at maximum frequency speed with a lower voltage. Recall that power usage is proportional to the square of the voltage, so a relatively small reduction in voltage produces big power savings and a lot less heat.

But wait, there’s more: look to the left of the graph where the I_off values are. The steeper slope of the NC-FET means less current flows when the transistor is switched off, which reduces the transistor leakage. Less leakage means less power use, resulting in better battery life and lower energy costs.

The steepness of the slope also influences transistor switching speed. A steeper slope means you can have a transistor that runs at a higher frequency, meaning faster CPUs.

Some Math for the Transistor Enthusiast

A mathematical explanation of the effect can be given by looking at the subthreshold swing, the inverse of the subthreshold slope.

The subthreshold swing is given by the following:

Where  is the semiconductor capacitance, is the ferroelectric’s capacitance, T is the absolute temperature, k is Boltzmann’s constant and q is the elementary charge.

If we plug our numbers into , which is the thermal voltage, we find it equals 25.85mV at room temperature.This value is considered a constant. Assuming a perfect body factor of 1, and multiplying by ln(10), we get a value of 60mV/decade, which is the minimum subthreshold swing for a traditional FET. However, it should be noted that if the temperature is reduced, so is S. This is why CPU frequency records are set with liquid nitrogen as the coolant.

The part of the equation in brackets is the called the body factor (, and it’s what we’re interested in.For a theoretically perfect traditional transistor,the body factor is 1,but the addition of a negative capacitance can lower it:

Where  is the gate voltage and  is the semiconductor’s potential.

A traditional insulating layer will have a positive capacitance, but if we have a negative capacitance insulating layer, then . If the insulator is less than zero, then , and thus the body factor can be . This enables S< 60mV/decade.

What Does the Future Hold?

The advantage of NC-FETs is that they don’t require a fundamental redesign of the microprocessor architecture. You can just whack a ferroelectric later onto the gate, and Bob’s your uncle, you have a chip with a lower power requirement. It’s so simple your cat could do it!

If companies are able to harness the negative capacitance regime of ferroelectrics, it would fundamentally alter the microprocessor landscape, resulting in lower transistor leakage current, lower voltages and thus much less power use. Batteries would last longer, data centers would need less cooling and electricity costs would go down. The cascade of changes would be enormous.

However, it is very early days, and these NC-FETs are unlikely to creep out into the real world anytime soon. There are still a few unanswered questions. Can the material change polarity fast enough to be used in microprocessors? They are in MHz. Can the ferroelectric layer be thin enough to sit on top of a >7nm transistor? It’s probably a little early to tell, but negative capacitance is something to keep an eye out for in the coming years, especially as progress in transistor scaling with major chipmakers like Intel is slowing. They have failed to shrink transistor sizes since 2014, and there is little sign of their new 10nm Cannon Lake making it into consumer products any time soon.

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