Si, SiC and GaN for Power Devices, Part Two: IGBTs, Si MOSFETs, Super-Junction Si MOSFETs and SiC MOSFETs

Which semiconductor is the power powerhouse? In this four-part series, we’ll take an in-depth look at the differences between silicon (Si), silicon carbide (SiC), and gallium nitride (GaN) to understand which is best for power devices and why.

In part one, we reviewed electron energy and semiconductors.

In part two, we’ll present a brief overview of legacy silicon devices like the IGBT and the power MOSFET. The power MOSFET was improved by using the super-junction MOSFET platform. SiC MOSFETs demonstrate capabilities well beyond those possessed by silicon.

Insulated gate bipolar junction transistors (IGBTs) served to replace silicon power MOSFETs in many applications. The power MOSFET is shown in Figure 7(a). Its input drive requirements are modest, but its output saturation voltage (established by R_DS(ON)) is only moderately low. The silicon power bipolar junction transistor (BJT) has a very substantial base drive requirement (see Figure 7(b)). The two devices are used together to create an IGBT as shown in Figure 7(c). The IGBT electrical schematic symbol (Figure 7(d)) emphasizes the MOSFET input and the BJT output.

Figure 8(a) depicts a small-signal n-channel, enhancement-only MOSFET (E-MOSFET). Recall that an E-MOSFET does not have a built-in channel. It is electrically induced by using a positive gate-to-source voltage (v_GS) that exceeds the threshold voltage (v_GS(th)). That is the voltage required to just form a channel of electrons between the drain and source regions (Figure 8(b)). The electrons are drawn from the heavily-doped n⁺ regions and minority carriers within the lightly-doped p^- substrate. The transfer characteristic and the drain characteristic curves are provided in Figure 8(c).

The transfer characteristic is affected by temperature as indicated in Figure 9. For lower levels of drain current, the drain current demonstrates a positive temperature coefficient (tempco). This means the drain current increases as the temperature is raised. At higher levels of drain current, the temperature coefficient becomes negative. The drain current decreases as the device temperature is elevated. The negative temperature coefficient means that MOSFETs can be connected in parallel. They tend to current share rather than current hog (like BJTs). However, at low levels of drain current, power MOSFETs behave just like BJTs. When connected in parallel, the hottest device draws the most current. This can lead to a catastrophic failure.

At elevated levels of drain current, MOSFETs are negative-temperature-coefficient devices. Therefore, as the temperature of the device increases, the device resistance increases. In other words, higher temperatures result in lower drain currents. This fact is important if you want to operate MOSFETs in parallel. With a good thermal path between devices, the negative temperature coefficient reduces the current in the hottest device and forces more of that current to flow through the cooler device, thereby avoiding thermal runaway.

Some engineers think of a MOSFET as a single power transistor, but it is a collection of thousands of tiny FET power cells connected in parallel (see Figure 10). In terms of sharing current, the same application of the negative temperature coefficient applies. In this case, the thermal path between the cells is better than that of separate packaged devices, because the cells are all on the same die.

Each hexagonal structure is one FET cell, and the individual cells are connected in parallel. For a given zero temperature coefficient point, this is where trouble can occur. If an engineer selects a device with a higher drain current rating, thinking it provides a greater safety margin, it could operate below the zero-temperature coefficient point. Consequently, hot spots can develop which could lead to device failure. Bigger may not be better.

Now let us look at a simplified representation of a planar vertical power MOSFET as shown in Figure 11. Two cells are depicted. The MOSFET has no doped-in channel as it is electrically induced. The structure is different than the small-signal (horizontal) version shown in Figure 8(b) but includes the essential elements. The voltage between the gate and source terminals establishes the channel induced through the p⁺ body regions. Basically, the channel serves as a valve. The valve is opened and controlled through the p⁺ source body region. The electron source is throttled by v_GS. The drain-to-source voltage v_DS controls the amount of drain current as permitted by the valve.

The individual source terminals are connected, as are the gate terminals. The drain connections are shared and therefore common and connected.

The planar power MOSFET is further detailed in Figure 12. The unbiased depletion regions are emphasized. Depletion regions are formed at the interface between n- and p-type semiconductors. The free electrons in the n-type semiconductor move across the interface to annihilate holes in the p-type semiconductor. The donor (electron-contributing) atoms in the n-type region become positive ions while the acceptor (electron-receiving holes) atoms in the p-type region become negative ions. The depletion region is termed that because it has been depleted of majority carriers.

Figure 13 illustrates a biased planar power MOSFET. The gate-to-source voltage establishes the channel. The drain-to-source voltage attracts negative electrons from the source terminal to produce drain current. The drain-to-source voltage also provides a reverse bias across the p⁺-n epitaxial layer p-n junction. The resulting depletion region is indicated by the dashed line. The corresponding electric field intensity in shown to the right. It is zero at the p-n junction interface and increases linearly as the ionization (depletion region width) increases.

The depletion region provides resistance to the flow of drain current. It contributes a resistance component to the drain-to-source on resistance R_DS(ON). As the drain-to-source voltage is raised, depletion region width increases, which increases R_DS(ON). The attendant electric field intensity increases. If the electric intensity becomes too large, avalanche voltage breakdown can occur. (Recall that avalanche breakdown means the electric field is strong enough to rip electrons from their parent atoms. This results in many free electrons. The current can increase dramatically.)

The depletion region extends into a semiconductor as a function of the doping level. That means it extends slightly into the heavily-doped p⁺ source/body region compared to its deeper penetration into the moderately-doped n epitaxial region. As the amount of reverse bias increases, the depletion region width increases. The depletion region width increases to “uncover” more ions to counter the applied reverse bias. Figure 13 illustrates the effective depletion region.

To permit the planar MOSFET to operate at higher voltages, it is necessary to more lightly dope
(n^-) the epitaxial layer. This increases the depletion width which reduces the electric field intensity. The trade-off is the more lightly-doped epitaxial layer will have more resistance which increases R_DS(ON). There are three components to R_DS(ON) as described by Equation (1).

The resistance of the channel, the epitaxial layer, and the substrate determine R_DS(ON). These resistive components are depicted in Figure 14.

The effects of the voltage rating on the resistive components are given in Table 2.

At a BV_DSS (Breakdown Voltage from Drain-to-Source with the gate Shorted to the source terminal) of 30 V, the three components of R_DS(ON) are about equal. When the rating is increased by lowering the doping concentration of the epitaxial layer, its contribution is increased to about 88 percent. At a rating of 600 V, its contribution dominates at 96 percent.

Power MOSFETs based on super-junction technology have become the industry norm in high-voltage switching converters. They offer lower R_DS(ON) and minimize its dependence on the BV_DSS rating. With “regular” planar power MOSFETs, the number of cells or the die size is increased to improve the BV_DSS rating. Both approaches increase the device input and output capacitances. When we recall the basic “Ohm’s Law” for capacitors (given by Equation 2), we are reminded that charge (q) is dependent on the capacitance (C) and the voltage (v) across that capacitance.

The efficiency for a power device depends on how quickly and crisply it can switch at any given frequency. The input and output charge must be removed and replaced quickly. This assures rapid transitions between ON and OFF. Once again drawing on basic theory, we see removing and replacing charge is a matter of the required current. We take the time derivative of both sides of Equation 2. Substituting the definition of current (i) produces Equation 3.

The planar MOSFET and the super-junction MOSFET platforms are contrasted in Figure 15. Figure 15(a) shows a planar device. The epitaxial layer is a lightly-doped n^- region. The depletion region extends into the epitaxial layer. The depletion region depth of penetration helps establish the device blocking voltage capability. The electric field intensity is greatest at the p-n junction interface and decreases to zero at the edge of the depletion region. This produces a linear decrease in the electric field intensity (the slope is determined by the doping concentration). Recall the lightly-doped epitaxial region yields a larger R_DS(ON) value. The blocking voltage is given by the area under the electric field intensity graph as indicated in Figure 15(a).

Figure 15(b) describes a super-junction device. The p⁺ source and body regions have been converted to wells. This modifies the overall depletion region. Observe the epitaxial layer now has a lower resistance n doping level rather than n^-. This permits a lower R_DS(ON) value. The electric field intensity is more uniform. This means the breakdown voltage is under better control. Further, while the super junction MOSFET can have the same R_DS(ON) value as a corresponding planar device, the chip size of the super junction MOSFET can be smaller. The smaller chip size means the input and output capacitances will be reduced. The super junction MOSFET can therefore operate at higher switching speeds. The smaller capacitance means reduced input and output charges. Hence, the device offers more efficient switching.

The electric field intensity (volts per micrometer) versus the epitaxial depth (distance in micrometers) is provided to the right of the two structures. The area under the two curves is equal to the blocking voltage. (Sure, (V/µm)(µm) = V). It is easier to make a comparison by redrawing the electric field intensity diagrams as illustrated in Figure 16.

Silicon carbide (SiC) MOSFETs offers significant performance advantages over silicon super-junction MOSFETs. The SiC MOSFET delivers an outstanding improvement in high-frequency switching power converter applications. Other than improved switching efficiency, higher operating frequencies, smaller size, and superior thermal characteristics, the planar SiC MOSFET has a structure like that of a planar Si MOSFET. The two platforms are given in Figure 17.

Figure 17(a) suggests the Si planar MOSFET die must be considerably thicker than the die of the SiC planar MOSFET. The SiC material has a much higher critical breakdown voltage than Si, allowing for a thinner drift layer and higher doping concentration. This leads to lower on-resistance for a given die area and voltage rating, providing for greater efficiency through reduced power loss. Additionally, SiC has a thermal conductivity more than three times better than Si, enabling the use of smaller die for the same temperature rise. SiC also provides efficiency improvements over Si by having higher maximum operating temperatures, limiting device stress. From a system standpoint, SiC may require less heatsinking, which means a smaller, lighter package is possible.

High converter switching frequency is a desirable characteristic because associated components, particularly magnetics, can be smaller, yielding miniaturization benefits and cost savings. However, switching losses in all devices scale directly with frequency. For instance, IGBTs are rarely operated above 20 kHz. This is because of power loss due to the “tail current” through the necessary snubbers and the charge and discharge of high device capacitances.

Si-MOSFETs can switch at hundreds of kilohertz, but energy is stored in output capacitance. The circulating current required to charge and discharge that output capacitance becomes a limiting factor as frequency rises. SiC delivers much higher electron saturation velocity and much lower capacitances, providing substantial benefits in higher speed switching and decreased power loss.

The characteristics of devices operating in the third quadrant are also of importance. This occurs when the conducting channel is reverse biased. This happens in hard switching applications. IGBTs do not conduct in reverse so an anti-parallel diode is required, which must be a fast recovery type with a low voltage drop. Si- and SiC-MOSFETS have inherently fast body diodes. These MOSFETs can conduct through their body diodes with low loss and no reverse recovery effect when switched ON via their gates.

Dead time (not to scale) is illustrated in Figure 18. The circuit represents a portion of a basic half-bridge buck converter that employs hard switching. We have two MOSFETs in series. By design, they alternate in conduction. Even though SiC MOSFETs switch rapidly, they do take a finite time to go from ON to OFF. Similarly, the opposite MOSFET switches from OFF to ON.

A significantly large current will flow from the power rail to ground if both MOSFETs conduct at the same time. This is called shoot through. To avoid this possibility, dead time is introduced. Dead time means both devices are OFF at the same time.

During dead time a MOSFET is reverse biased. This means the source terminal is positive relative to its drain terminal. This causes its body diode to conduct. A significant power loss is incurred because of  the diode’s relatively high forward voltage drop. In Figure 18(a) Q₁ is operating in the first quadrant. The drain is positive relative to the source terminal and drain current flows into Q₁. In Figure 18(b) transistor Q₂ is operating in the third quadrant since the drain is negative relative to the source terminal and drain current flows out of Q₂.

Insulated gate bipolar junction transistors (IGBTs) served to replace silicon power MOSFETs in many applications. Their saturation output voltage is less than the R_DS(ON) voltage drop of many silicon power MOSFETs. However, the maximum IGBT switching frequency is about 20 kHz. Enhancement only MOSFETs do not have a doped in channel. It is electrically induced by the gate-to-source voltage. Its transfer characteristic has a positive temperature coefficient of drain current at low values of drain current. The transfer characteristic exhibits a negative temperature coefficient of drain current at high values of drain current. At high levels of drain current, FETs tend to current share rather than current hog. This means they can be connected in parallel without concerns of failure. This notion is extended to power MOSFETs. They are comprised of many individual cells that are connected in parallel.

The planar power MOSFET uses a vertical structure. This means the electron path through the drift region is relatively short. This promotes low values of R_DS(ON).  It is an enhancement-only device. Positive values of gate-to-source voltage induce a channel (like a valve) the permits electrons to flow through the p⁺ body region. To increase the blocking voltage without entering avalanche break down, the depletion region must be wide. To permit the planar MOSFET to operate at higher voltage the epitaxial layer must therefore be more lightly doped. This increases the depletion region width and that reduces the electric field intensity. The light doping also means R_DS(ON) will increase and that produces greater losses.

The super-junction MOSFET is designed to permit operation at high voltage levels and achieve low values of R_DS(ON) simultaneously. The p⁺ body regions are fabricated as deep wells. This modifies the depletion region, so the electric field intensity is more uniform. Higher voltage ratings, with low R_DS(ON) values are possible and achievable using a smaller die. The smaller die means the device capacitances are reduced, which elevates the switching speed capability.

The Si planar MOSFET die must be considerably thicker than the die of the SiC planar MOSFET. The SiC material has a much higher critical breakdown voltage than Si, allowing for a thinner drift layer and a higher doping concentration. Consequently, with SiC, higher voltage ratings and low R_DS(ON) values are possible. SiC planar MOSFETs are also much faster than silicon devices because of the SiC wide bandgap, and large saturation velocity. SiC devices operate well when experiencing high temperatures.

In a circuit like a half-bridge buck voltage regulator, two MOSFET power switches are connected to form a path from the positive power rail to ground. It is critical both switches do not conduct simultaneously. To do so would produce a shoot-through event that could cause the switches to fail catastrophically. To avoid this both switches are held OFF briefly. This is called dead time.

In our third installment, we will look at GaN-based devices. There are two rival configurations to be investigated: the cascode arrangement and the E-HEMT (Enhancement High Electron Mobility Transistor).