The Future of the Semiconductor Industry Depends on Testing

Many economists and futurists have stated that semiconductors will be in the 21st century what oil was in the 20th. As a critical enabling economic input, semiconductors, particularly processors and memory, will largely determine the future of companies and nations. As supply chains are shifting from global to regional, this decade is seeing an unprecedented reshoring of semiconductor manufacturing to the United States.

Patrick Sullivan: Hey, thanks for having me.

Jim Anderton: This is such an important topic and it's so important right now with what we're seeing with the semiconductor industry in general. Semiconductors and especially processors memory, this has become a geopolitical issue. We hear talk in popular press about the vulnerability of Taiwanese operations and then heightened commercial competition with China and this reassuring that I referred to that's coming to America. But we also hear about how expensive and time-consuming it is to set up fabs, to get lines up and running. Is that true also of the way that we test these products there? Does it take this kind of time a year, two years to get set up to test the product?

Patrick Sullivan: Yeah, so the test for a particular chip is developed in parallel with the chip design. And in fact, a lot of the vectors that are used to verify the chip in software before it's manufactured are used to develop the test program. So if the technology is present, in other words, the pin electronics are fast enough, the DPS is sufficient, it can be the test solution can actually arrive pretty quickly. The development of pin electronics, device power supplies and such, those are ongoing. So we're actually looking many years into the future and talking with our customers and our customers' customers to see what their needs are so that we can plan an appropriate product for the upcoming technology.

Jim Anderton: At the very beginning of IC semiconductors, all devices were general purpose because there are a limited number of devices basically. So you assembled your product out of basic gates and you built something. But you know what, if you needed a quad end, that's what you ordered from Motorola or Texas Instruments and you assembled your board. Then we moved to an era of general purpose semiconductors when you could just basically go to software and use an 8088 under the hood of everything. They'll run everything from an automotive application to an autopilot. Today, we're seeing a new generation of fabs making custom devices for specific applications, and I'm thinking here, not just military but for example, medical or aerospace where... so in that respect, now we've got a much broader variety of very, very specific devices. Do these custom special purpose ICs, do they present a different challenge for testing?

Patrick Sullivan: Absolutely. So I'll start by the predominant technology is the smaller and smaller geometries, 5 nm and below, and those present a tremendous challenge in the speed of testing. So the density of pins really require that you develop new ICs that go into the testers that can provide the density necessary, and then also power efficiency. So the device power supply has to be tremendously efficient. You have a limited amount of power coming into the test board, and then that power, you want to deliver a hundred percent of that to the device under test. And so very efficient device power supplies are needed for those and they can go a thousand amps, so we're talking huge, huge power. On the processes that I believe you're referring to in your question are more like for automotive. So higher voltage, there's other exotic processes that they're coming up with.

And so we've actually come up with a chip called the Whitney, which is significantly higher voltage than traditional ATE, which typically is around 15 volts. We're actually going plus and minus 65 volts, and we'll actually use that architecture to push higher and higher voltages to try and meet the demand that's coming from things like silicon carbide, gallium nitride, and other high voltage processes. Also, what they're trying to do is increase the complexity of these high voltage devices so that the device that's being sold is significantly more complex and integrated unlike the NAND gates that you discussed earlier.

Jim Anderton: Now, I want to loop back to the new materials question. But you mentioned gate dimensions, the size of the device is 7 nm, 5 nm. Now, I know the mass media tends to think of these things as literal dimensions, and of course, it's fairly loose the actual definition of what a 7 nm or 9 nm dimension really means. But some experts claim that the infant mortality will be higher every time we go to a tighter gate dimension like this.

And that for mass production devices, this is going to be a problem. If your idea for high speed testing is to use a go/no-go methodology basically and just run the thing at high speed with two, three seconds of test time or less and then go through. Some are also saying that we may see what we have seen with memory devices in a world where there's no such thing as a go/no-go. But there are A grade, B grade, C grade devices and your pricing and your customer will purchase the level of, "Quality," that they need for their application. Do you see this as the future of the industry?

Patrick Sullivan: Yeah, I mean, typically with infant mortality you have to do some sort of a burn-in, and one of the big problems with some of these smaller geometries is the tolerances are so tight. So if you're down at nine-tenths of a volt, your device power supply has to be very accurate to force exactly nine tenths of a volt. And what happens is if you get glitching on there where it bumps up, you could actually be inflicting some damage and creating a device that's a walking wounded, so it'll go out in the field and die early. So this is just starting to happen for us. 

We're starting to see results and so we're really getting pushed by our customers to make sure we have very low voltage, very high accurate device power supplies that don't actually... when you go from zero amps to a thousand amps, you don't want that voltage to move. Now, that's virtually impossible, but if it does move, you could actually think that your device failed because if something reset in the part due to that huge spike. And if it goes above, you could be damaging the device. So there's a tricky problems to solve to enable 7 nm, 5 nm technologies to be tested efficiently.

Jim Anderton: Yes. Those voltages you're talking about are pretty high. I almost think how the mechanical engineers could come in here. If you're testing one device every 60 seconds, you can drop into zero insertion force socket, flip the lever, and you're going to get consistent sort of clamp force across the contacts on the pin outs. But you're talking about different world now, you're talking about automated testing, essentially you're talking about very, very low voltages. Even things like contact resistance or just the amount of physical pressure you use between a contact pad and all these things suddenly come into play. Does that complicate the problem on the software or the hardware side for testing?

Patrick Sullivan: Absolutely. And one of the things we do have is remote sensing, you can get current sharing issues, especially if you have these impedances. But in our parametric measurement units and our device power supplies, we always have a remote sense. So you can actually take a pin on the pad and use that as a sense point. You can actually even sense the metal on the device under test, so you can ensure that the voltage at that point is correct.

Jim Anderton: Now, I think back, there a power semiconductors, which is something I love, something in my history and I love a MOSFET in a T03 case. It's like the size of a quarter basically, grand old days Micah insulators. But power semiconductors historically have been relatively easy to test. You load them, you cycle them, then maybe use statistical sampling methodology, and then you might test something to destruction or test it to failure. And then using SPC techniques here, you could be pretty sure you're shipping a good device. But with the increasing sophistication of these digital devices, and now we've got a lot of code needed to drive automated testing, how much production runtime can a manufacturer allocate to testing? If these things are coming like sausages off the end of the line that says basically, can you afford to drop the unit into the machine for seven or eight seconds to test it? 

Patrick Sullivan: Yeah, I mean, that's actually a big problem. Everyone has been pushing to bring down the cost of test by initially bringing down the cost of pin electronics. It used to be a channel was $2,000 and now it's significantly less, around a hundred dollars a channel. And the goal has always been to do it in the hardware, but the reality is test time now with these incredibly complex chips is going through the roof. And so there has to be... and a lot of them actually, especially in the 5 nm stuff, you actually test it and you have to do a dual insertion, typically a system level test after you've done your ATE test.

So now there's even more testing. And so some of the things that we're looking at doing is bringing... you have limited test vectors and to do a system level test, you could never do it on a standard ATE, it would take a long time. So we're actually looking at things like having emulators behind the pin electronics, emulating protocols, things like that to enhance the tester's ability to run these tests very rapidly. But it's a huge challenge. They always wanted... test cost used to be about 30% of the cost of a chip and everyone thought it was going to come down and it started to. And then with these new technologies, it starts creeping back up and that's the big problem.

Jim Anderton: Now, you mentioned earlier about gallium nitride and it's hot, everyone's talking about it. We keep bringing hearing it's the substrate, it's the material of the future, high band gap, faster switching, higher thermal conductivity, lower resistance. I mean, it's everything. It's like perfection in material, the way they talk about the thing, and it sounds terrific. Are there going to be challenges in testing a new generation of gallium nitride devices, do you think?

Patrick Sullivan: Yeah, I think if you look at... and we've actually looked at some of these technologies to create. So that's the one thing about test, that we don't get a lot of glamour, but we do have to investigate all these technologies and we have to test chips with the same technology and sometimes actually less technology than what's out there. So we have investigated gallium nitride for our own use. We've looked at silicon carbide and we will probably have some products that roll out for higher voltage using those devices as output stages. The challenge, you look at silicon carbide and gallium nitride with EVs, especially driving motors, the efficiency is so much greater with these very low capacitance, lower on devices.

And so these things are ubiquitous and silicon carbide in particular, one of the challenges is you have to burn it in to stabilize the VTs, the thresholds, and this is actually kind of a long process. And so the way around that is to just test a bunch of them in parallel and also to... as you add complexity to these devices for processing, you actually try and do what they call test during burning. So as the burn process gets longer and longer, you try to do more and more because it's effectively free time. So we're seeing a lot of that. We're seeing a lot of parallel tests and then more complexity adding into the burn-in machines to create this test during burn-in.

Jim Anderton: Okay. That's an interesting approach because historically of course, you'd like to burn-in first before you test, so you can just take care of the infant mortality problem and weed out the dead ones before you invest that testing time and energy in here. But is it a trade off then a question of we don't have the time, so let's do it at the same time?

Patrick Sullivan: Yeah, you don't want to have to do a dual insertion if you can get away with it. So testing on a more expensive tester is going to... they're all burned-in, but now you got to test on this expensive tester and that costs money. And so if what you're looking for is simple enough, and we've actually enabled a lot of this by driving down the cost of pin electronics, adding, integrating much more into our ICs, reaching back into the tester and trying to bring more stuff onto our Ics. And now we're enabling people who maybe weren't as sophisticated in the test domain to go ahead and develop these products.

Jim Anderton: Yeah. Now, yeah, of course, we're talking about... it's like a game of inches, it's a game of seconds. Testing, we want to cut that time as much as possible to keep cost under control. And we're also of course, seeing a world where software enabled products are the future and less and less of these things are actually wired into hardware. Whereas, we used to worry about the speed of light we can get current through, run a conductor about that long. Now we're talking about what the runtime is of the software that operates the test there. How much in automated testing now is software limited versus hardware limited?

Patrick Sullivan: Yeah, I think most of it is in the software. So especially with these very complex chips, there's a bunch of set up and so that's where we think we can help out. Adding more and more in the hardware, bringing some of that stuff that is typically found, things like protocols, things like even emulating processors or something like that. To be able to go ahead and talk directly in hardware to a device and do more system level tests during the ATE test eliminates the need to format all these vectors and pump these through.

There has been... design for tests and scan insertion and things like that have helped a lot with mitigating how many vectors are needed. But then all of a sudden the complexity of the devices go up and now you have longer scan chains or more and more scan chains in parallel really, which also then drives up your need for high speed IO. So yeah, it's definitely a problem, it's something we're trying to help solve. We're not really as involved in it. It's really our customer's issue that they're dealing with, but wherever we can help make the tester better, we try to.

Jim Anderton: I come from the automotive space, automotive electronics and the tendency of our OEM customers were to think about production processes from a mechanical engineering perspective. So qualifying testing devices involved things where they would want to see something traceable back to National Bureau of Standards or something. Or give me a qualified standard and show me the paperwork to say that you have tested your tester against that standard. How does that work with automated chip testing at this point? How do you validate the testing process?

Patrick Sullivan: So there is a calibration that goes on. So the machines have built-in calibration and so that's typically done on a monthly or quarterly basis to... anytime you're calibrating, you're not testing parts. And so the goal is not to calibrate very often if you can get around it. So are some... when you calibrate a machine, you record all the forced voltages, all the measured currents, and so you go through a full verification that the machine is accurate. Just like if you had an instrument like a DMM on your desk and you say, "Oh, is this really measuring the right voltage?" You have someone come in, we have people come in and calibrate all of our equipment in the lab on a pretty regular basis.

Jim Anderton: Is there a drift issue? Semiconductors that you supply, for example, for testing equipment, do these things have a life expectancy? I recall famously in color matching equipment with spectrophotometry, it was mandatory to, believe it or not, change the light bulbs in the quality control lab on a set schedule long before they burned out because the color temperature would drift. Is there something inherent and drift in semiconductors this way? Do you have to rotate them out?

Patrick Sullivan: So what we do is we do a qualification. We do a HTOL high temp operating life. And so what we do is we accelerate in temperature to mimic 10 years of life and that's what we guarantee. Every device, if you look at a CMOS device for example, and you run it close to the BGS or even maybe if you stress it a little bit above and you're running it for a time, you get something called time dependent dial electric breakdown. And so what'll first happen is you'll start to see some VT shifts in those devices, and then you'll start to see GM changes in those devices, and then eventually you'll start to see a leaky gate. So, we're very conscious of this, so when we design, we cannot afford to have a part that's out there that drifts over time because it would force our customers to have to recalibrate at maybe a more frequent level.

And it also throws into question whether their testers accurate enough to test the parts going out and is their customer actually shipping good product. So we're very conscious of that. We monitor it, we have our customers, we're in constant contact with our customers about any potential drift issues. And so we take this also into our design, into account in our design. So even if it's a closed loop design that sort of self-corrects, we want to make sure that nothing bad is happening in that device where it could all of a sudden die or drift.

Patrick Sullivan: And we have a product that actually was designed two companies ago and that I worked on and that product we're selling, we still have orders out to 2026, and that was designed in probably 2002. So to give you an example, these things stay out in the field a long, long time. So we have to make sure they don't drift and we haven't seen any major problems, so cross our fingers.

Jim Anderton: Patrick, now that you've mentioned it, one last question related to that. It's talked now about the time to market, time to develop, qualify these processes. For individuals out there who are designing automated test equipment and also for their customers for potentially fabs and people basically who are not necessarily perfectly versed in the technology of testing, but know they need test equipment. How far in a advance should they be thinking about this problem and what should they bring to a company like yours? What questions should they ask to get a project moving?

Patrick Sullivan: I mean, typically fabs and customers that use those fabs, we'll start a dialogue with their preferred vendor of testers and say, "Hey, this is where we're going. Make sure your tester stays on this technology path." So when we get there, we can actually test the product, produce the product. And it used to be you could just do a product and then say, "Well, we'll figure out the testing later," but you just can't do that. The times to market on some of these products are so... in the market window, you throw out a 5G chip and you might be able to sell that for a year and then it's something else that's out there or less. So you have to have a tester concurrently being built or modified, you can develop new instruments for an existing tester that will meet that technology demand.

So that goes on. People are thinking about smaller and smaller geometries. It's on their roadmap and it's been on their roadmap for many, many years. And then what happens is our customers tend to come to us and say, "Hey, we're developing a tester that's going to be for 5 nm stuff. We need to double our density of pin electronics. We need to have the power. We need to bring the voltages down. We need to in increase the accuracy." And then on the DPS side, we have to do all those other things that I mentioned, bring the voltage down, but make sure you can gang them together and pump out a thousand amps without an issue and then it doesn't move. It's a rock solid voltage. You can measure very accurately the currents, enforce very accurately the voltages.

And so they start pushing us on those specs so we have a notion of what's coming down the line well in advance. And then we have to go resource it and find the technology that we can hit these targets with, so we typically can't go out... the cost of a 5 nm mass set might be $10 million right now. And not to mention the wafers and trying to get access and the kind of volumes that we need, which are much smaller. We're not a company that fabs really go after for the business because of our volumes, but they know they need us. So we can't typically go into 5 nm, so we'll pick a technology that we can use to test a 5 nm and that's still reasonable and we can still get access to.

Jim Anderton: What a neat summary, it's a niche business, but an essential business for the entire semiconductor supply chain to operate.

Patrick Sullivan: Yeah. About 30 years ago when I was first starting, someone was talking about the ATE industry and they said, "It's a little bit like your sewer system. You really don't like to think about it. You don't like to put a lot of money into it, but when it's broken, you notice right away."

Jim Anderton: A neat analogy. Patrick Sullivan, Elevate Semiconductor. Thanks for joining me on the show.

Patrick Sullivan: Hey, thank you. I really appreciate it.

Jim Anderton: And thank you for watching. See you next time on Manufacturing the Future.