Stacked Chip Packages
In the modern smartphone, stacked chip packages abound. Many years ago memory manufacturers (DRAM and Flash alike) realized that the drive to higher densities could not be accomplished simply at the silicon die level. Standard packaging formats constrained the lateral dimension form factors. The solution adopted was to thin memory die and stack several (2, 4 or 8) together in a single plastic package.
Image courtesy Amkor Technology
System in Package
The next step in the evolution was the creation of system-in-package designs or SiP. This concept is slightly different since it entails the mixing of heterogeneous device types in a single package.
This had been done in a slightly different way in previous decades through the hybrid IC or multi-chip module (MCM). Those earlier attempts were typically expensive and therefore limited to aerospace, military or other low-volume applications. For consumer electronics, a low cost solution is always required. Perhaps more importantly, the idea of bundling several ICs or components together needed fresh marketing. Hence the SiP was born.
Here's a list of SiP components in a today's cell phone:
- eMMC – NAND flash memory (multiple stacked) die with MCU on top for wear leveling and bus interface
- Applications processor plus DRAM (two stacked die or four) in package-on-package (P-o-P) configuration
- Smart MEMS – gyro or accelerometer with stacked (or adjacent in certain cases) digital die for interface to applications processor
- MEMS oscillator and digital controller chip
Although all these devices serve a critical role in reducing logic system board space, they do not address the future integration challenges of maintaining Moore's Law. The next generation of stacked and SiP devices will use through-silicon vias (TSV) to interconnect adjacent die with a higher density system of vertical wiring.
TSV has not made it into the low-cost chip applications like smartphones as yet. So far it's limited to the high-end applications, particularly very wide I/O. Furthermore, the interconnections such as the Xilinx FPGA are side-by side using passive silicon interposers.
Moore's Law is nearing exhaustion
Current mobile chips allows some motherboard space savings so that more functionality can be crammed into handheld form factors. But none of the current mobile chips is changing the game.
And the game needs to change before the final whistle blows.
Moore's Law as it has been known is nearing exhaustion. For decades, the law of semiconductor land was actually kept by Sherriff Dennard. You see, Dennard's law was related to dimensional scaling of planar devices.
Each new technology generation created smaller transistors that allowed higher device counts on chips per unit area leading to higher performance, greater complexity and enhanced functionality over time.
Slide courtesy Intel (Mike Mayberry presentation)
But very soon after the turn of the last century, dimensional scaling alone could no longer cope with the demands for higher performance. Materials science regained prominence as aluminum gave way to copper wiring and strain engineering was required to quite literally squeeze more performance out of CMOS transistors.
There are many proposed solutions to keep Moore's Law on track. Unfortunately, solutions like extreme ultraviolet (EUV) or other so-called next-generation lithography tools are complex and costly. Reservations about the high cost has had the knock-on effect of delaying development as industry players delay investment as long as possible.
Enter monolithic 3D
There is 3D and then there is monolithic 3D. Integrating several active layers together and then incorporating a common set of global wiring has the potential to re-invigorate Moore's Law. Not only that, but the approach is less complex and costly than dimensional scaling and even offers an opportunity to trailing edge semiconductor foundries to stay relevant.
There is an interesting start-up devoted to the development of true 3DICs that takes its name directly from the approach – MonolithIC 3D™ Inc. The San Jose company, led by founder and chief evangelist Zvi Or-Bach, is leading the charge for pushing the chip industry aggressively into the third dimension.
With industry giants like Intel and TSMC needing a viable alternative to scaling, who knows what future smartphones will be capable of once they adopt true 3DIC technology?