Texas Instruments has sponsored the following story
I just read a white paper about designing small cell base stations that highlights the potential gains from digital radio front-end advances. By way of background, wireless operators are faced with changing network infrastructures because of the mushrooming growth in data usage which requires increased capacity, reductions in cost and heterogeneous networking with co-existing macro cells and small cells in the network. This shift creates a challenge for small cell designers as they need to address the conflicting goals of low power consumption, small footprint and lower cost while still delivering amplification boost in performance.
A key service delivery mechanism to support these infrastructure changes is the move towards more cost effective and smaller footprint indoor and outdoor cells that fit between larger macro or metro cells and much more limited residential or femto cells. Indoor enterprise and outdoor pico cells will play a key role in bridging the gap between wide-area and residential footprints.
Design Challenges for Small Cells
A number of challenges confront the small cell designer, some of which are in the design of the Digital Radio Front End (DRFE). For example, one challenge is reducing the system's peak-to-average ratio (PAR), which will reduce the system's overall power consumption. This in turn leads to smaller component size, reducing the overall component cost and BOM. One way to accomplish this is to use Crest Factor Reduction, which is a signal processing algorithm that is used to reduce the systems PAR.
Another DRFE design challenge is providing a more linear performance from the systems PA (Power Amplifier). The power efficiency of PAs move away from a linear performance line as the device nears its peak driver point. If the PA is not operating efficiently, it causes the system to waste power and generate excessive heat. One solution to this problem is Digital Pre-Distortion (DPD), which allows a more linear performance as it reaches its peak drive point.
Still another design challenge stems from the communication links between ADCs, DACs, FPGAs and DSPs in the overall system. The designer's goal is a high throughput low pin-count interface, which increases performance and allows for fewer lanes on the board. Implementing the JESD204B is one way to accomplish this. The JESD204B standard embeds the clock into the data stream, simplifying system design and using less lanes on the board.
KeyStone Based SOC
TI has developed a device that addresses these design challenges in a SoC. TI's TCI6630K2L SoC is a high performance, low power solution for enterprise PoE+ small cells and outdoor pico deployments. The TCI6630K2L is based on TI's high-throughput KeyStone II architecture. This SoC is a scalable low-power baseband solution with an integrated digital radio front end (DRFE). It meets the power, size and bill of materials pricing needs of small cell wireless base stations. The devices' dual ARM/quad DSP cores deliver the processing power needed for enterprise and pico base stations.
The TCI6630K2L scales TI's previous generations of wireless SoCs and transforms them to the special requirements of small cell base stations. The KeyStone II architecture provides scalability for the use of small cells, from indoor enterprise to outdoor pico cells. Software developed for any KeyStone-based device is scalable upward or downward for any KeyStone SoC. Software development can be reduced by re-using code.
Up until now, most base station devices have used discrete DRFE implementations. The TCI6630K2L is the first wireless infrastructure SoC to incorporate an on-chip DRFE. This allows the TCI6630K2L to meet the low power, lower cost and reduced design requirements of small cells. By incorporating the DRFE on-chip, the TCI6630K2L combines the control, baseband and DRFE into one processing unit.
The DRFE section of the TCI6630K2L incorporates the CFR algorithm to reduce the PAR of the system, thus reducing component cost and BOM. In addition, it uses DPD to lower overall power consumption.
The TCI6630K2L incorporates a new serial communications interface based on the JESD204B standard. This improves system throughput and requires less lanes on the circuit board. In addition, the TCI6630K2L implements a Multicore Shared Memory Controller (MSMC), which allows cores to directly access the shared memory in the system. The DDR3 external memory interface (EMIF) of the TCI6630K2L consists of one 1600MHz, 72-bit bus that supports as much as 8GB of addressable memory space.
The TCI6630K2L SoC also has two HyperLink interfaces for high-speed communication between KeyStone devices. Each hyperlink can support a bandwidth of up to 100Gbps.
TI's TCI6630K2L provides small cell designers with many features that increase performance, reduce system design time, reduce power consumption and BOM, and significantly lower the overall cost of bringing small cell designs to market.
Texas Instruments has sponsored promotion of their small cell solutions on ENGINEERING.com. They have no editorial input to this post - all opinions are mine. Randy Boulter