Universal Verification Methodology (UVM) is a process used to verify the design of integrated circuits. It is designed to automate the SystemVerilog language which is used to describe and verify electronic hardware.
Accellera Systems Initiatives is a not-for-profit organization that produces system-level verifications, designs and models used by the electronics industry. Mentor Graphics looks to work with Accelera to improve the UVM process using updated GBTS standards to outline the work flow of the verifications.
GBTS format has been used for years, helping to automate compiler testing. It is based on IBM’s Backus-Naur Form standard.
John Lenyo, VP at Mentor Graphics said that, “Having access to the most advanced functional verification methodologies is essential to maximize electronic design and verification efficiency, and we have seen customers realize a ten-fold gain in productivity through the adoption of graph-based test technology … Based on customer feedback, we’re moving forward to recommend and facilitate a standards effort that brings significant benefits to a large number of users, and opens the door to technology innovation.”
Mentor states that their method can reduce coding by 50% or more while maintaining test intent. As coding is reduced so is the debugging process, allowing designers to focus on fixing designs as opposed to testing.
GBTS also allows for the use of multiple design languages and verification environments. This means that the format can be reused for design context and verification engines. SystemVerilog UVM for block-level simulation, C test programs for system-level emulation, microprocessor instruction set verification, and even FPGA prototyping and post-silicon validation can all use the same graph-based test specification. Some other languages supported by the GBTS include Verilog, VHDL, e, SystemC, C++ and assembly code.
Additionally, the GBTS is abstract enough that tool implementations can run a set specification in various ways as dictated by the verification requirements. A tool can therefore be instructed to perform a test in a systematic way and later be told to perform the test specification in a random order.
“The Mentor graph-based specification technology brings compelling new value to the verification domain with its capabilities for quickly and exhaustively covering the device state space … This lets us use a unified graph-based description for traditional coverage-driven verification using UVM at the block level, as well as intelligent software-driven verification using embedded C test programs at the system level,” said Peter Jensen, owner of SyoSil an electronics consulting company.
Source Mentor Graphics
Reference Accellera