Designers can use these solutions with the Veloce emulation platform to assess their device integrated into a System-on-Chip (SoC) designs. Additionally, users can develop and stress-test both their software and hardware with billions of cycles.
Multimedia devices and networking infrastructure need a lot of memory bandwidth. Therefore, the Velcro 2 emulator is now able to speed up models for emerging memory standards.
HMC is a 3D-DRAM architecture it can:
- Bring memory bandwidths > 100Gbits/second (15x DDR3 memories)
- Consume 70% less energy/bit (compared to DDR3)
- Be used with increased networking requirements, CPU and GPU bandwidth
LPDDR4 and eMMC 5.0 memories are used in conjunction for mobile products as DRAM and mass storage respectively. They deliver reduced power, cost and form factor.
The memory modules can be used plug-and-play style with the design running on the Veloce emulator. They are also compatible with the Questa functional verification platform when moving from simulation to emulation.
Eric Selosse, VP and GM of Mentor's Emulation Division, says,“Our ability to provide industry-leading solutions for the verification of SoC designs containing next-generation memory devices is critical to the success of our customers developing high-performance products ... In delivering these new memory device solutions for emulation, Mentor has again demonstrated our leadership as the premier supplier of hardware-assisted products for SoC verification, and our commitment to providing customers with the best-in-class emulation solutions for the latest-generation standards.”